Today's SoC designers need to incorporate PCIe 7.0 into new AI chip designs. Primary streaming success is critical to meeting the growing performance and bandwidth demands of data-intensive applications.

Data center technology needs to evolve to support the growing workloads and demands of AI, especially as the number of parameters doubles every four to six months - four times faster than Moore's Law (Meta, 2023). Current AI models have trillions of parameters, pushing existing infrastructure to its limits. As a result, more capacity, greater resources, and faster interconnections are needed.

According to Synergy Research Group, the global capacity of hyperscale data centers will more than double in the next six years to meet the demand for generative AI. To meet this growing demand, The data center ecosystem relies on standards such as Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Ethernet, and High Bandwidth Memory (HBM) to provide the performance, capacity, bandwidth, and low-latency frameworks needed to transfer data throughout the system.

For data center chip design to be successful, fast and efficient interconnections and interfaces are critical. Designers need faster performance and zero latency; The ability to transmit large amounts of data; And access to an advanced interface IP that not only provides bandwidth and energy efficiency, but also maintains interoperability with a complex and evolving ecosystem.

To meet these requirements, data center interconnect needs to support PCIe 7.0, the latest specification for this critical standard. While the standard has not yet been approved, it is important to integrate PCIe 7.0-enabled IP into the chip roadmap now, especially given that today's chips take a year or more to produce.


The next leap in performance

PCIe 7.0 is ready to deliver the bandwidth needed to enable the scaling of hyperscale data center interconnection. PCIe 7.0 provides fast, secure data transfer at up to 512 GB/s, essentially future-proof data center bandwidth to ease data bottlenecks.

With the support of interface IP, high-speed interfaces (such as those on processors, accelerators, switches, etc.) can move data between cpus and accelerators, as well as between entire computing structures (including retimers, memory, switches, network interface cards, etc.). Compared to PCIe 6.0, PCIe 7.0 increases the number of supported channels and doubles the bandwidth. By increasing signal transmission rates, PCIe 7.0 also reduces latency, which is critical for real-time processing and responsiveness in AI algorithms and high-speed data processing in high-performance computing (HPC). Of course, PCIe 7.0 also maintains backward compatibility with previous generations of PCIe, ensuring interoperability with existing hardware while providing scalability for future upgrades.


Maintain critical interoperability

The beauty of interoperability (and mature standards like PCIe) is that it enables a range of vendors in different ecosystems to collaborate and ensure that their respective components/systems operate reliably with each other. When designing the world's fastest chip, it is necessary to ensure seamless operation for a long time. When all parts are interoperable, there is no need to worry about excessive downtime or other performance issues.

Before designing a system, or even before selecting any IP, designers should go through an exhaustive evaluation process. With PCIe, there are many variants, channels, media, form factors, and ranges to consider. For example, these designs often require many high-speed lanes. Multiple PCIe switching channels consume a lot of power at the same time, making power integrity an issue. If problems such as IR pressure drop occur during simultaneous switching, overall performance will be inhibited. Signal integrity analysis (Figure 2) is also important because the signals transmitted between the AI accelerator and the CPU in the system must be intact. This, in turn, will make power and signal integrity expertise critical for engineers to understand how to achieve optimal performance.


Why choose PCIe 7.0 today?

Future AI clusters (including accelerators, switches, network interface cards, etc.) must be able to be deployed simultaneously to enable data-intensive operations and alleviate data bottlenecks. Getting an IP that supports PCIe 7.0 before the standard is approved is critical for companies to start the next HPC and AI chip designs as early as possible, and to be confident that when these chips are deployed, they will deliver the bandwidth and performance required by the world's fastest chips.